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Preliminary Technical Data
FEATURES
Dual 14-bit SAR ADC Simultaneous sampling Throughput rate: 4.2 MSPS per channel Specified for VDD of 2.5 V Power dissipation: 35 mW at 4.2 MSPS On-chip reference: 2.048 V 0.25%, 6 ppm/C Dual conversion with read High speed serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible -40C to +125C operation Shutdown mode: 10 A maximum 16-lead TSSOP package
Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC AD7357
FUNCTIONAL BLOCK DIAGRAM
VDD VDRIVE
AD7357
VINA+ VINA- REFA T/H 14-BIT SUCCESSIVE APPROXIMATION ADC SDATAA
BUF REF BUF CONTROL LOGIC SCLK CS
REFB VINB+ VINB- T/H
14-BIT SUCCESSIVE APPROXIMATION ADC
SDATAB
AGND
AGND
REFGND
DGND
Figure 1.
GENERAL DESCRIPTION
The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide bandwidth track-and-hold circuit that can handle input frequencies in excess of 110 MHz. The conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. The AD7357 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 2.5 V supply and a 4.2 MSPS throughput rate, the part consumes 14 mA typically. The part also offers flexible power/throughput rate management options. The analog input range for the part is the differential common mode +/- VREF/2. The AD7357 has an on-chip 2.048 V reference that can be overdriven when an external reference is preferred. The AD7357 is available in a 16-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions. These functions allow simultaneous sampling and conversion of two channels. The conversion result of both channels is simultaneously available on separate data lines or in succession on one data line if only one serial port is available. High Throughput with Low Power Consumption. The AD7357 offers a 4.2 MSPS throughput rate with 35 mW power consumption. Simultaneous Sampling. The part features two standard successive approximation ADCs with accurate control of the sampling instant via a CS input and once off conversion control.
2.
3.
Table 1. Related Devices
Generic AD7356 AD7352 AD7266 AD7866 AD7366 AD7367 Resolution 12-bit 12-bit 12-bit 12-bit 12-bit 14-bit Throughput 5 MSPS 3 MSPS 2 MSPS 1 MSPS 1 MSPS 1 MSPS Analog Input Differential Differential Differential/Single-Ended Single-Ended Single-Ended Bipolar Single-Ended Bipolar
1
Protected by U.S. Patent No. 6,681,332.
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07757-001
AD7357 TABLE OF CONTENTS
Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Analog Input Structure.............................................................. 12
Preliminary Technical Data
Analog Inputs ............................................................................. 13 Driving Differential Inputs ....................................................... 13 ADC Transfer Function............................................................. 14 Modes of Operation ....................................................................... 15 Normal Mode.............................................................................. 15 Partial Power-Down Mode ....................................................... 15 Full Power-Down Mode ............................................................ 16 Power-Up Times......................................................................... 17 Power vs. Throughput Rate....................................................... 17 Serial Interface ................................................................................ 18 Application Hints ........................................................................... 19 Grounding and Layout .............................................................. 19 Evaluating the AD7357 Performance ...................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
11/08--Revision PrF
Rev. PrF | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
AD7357
VDD = 2.5 10% V, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, fSCLK = 80 MHz, fSAMPLE = 4.2 MSPS; TA = TMIN to TMAX1, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms ADC-to-ADC Isolation CMRR SAMPLE AND HOLD Aperture Delay Aperture Delay Match Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Positive Full-Scale Error Positive Full-Scale Error Match Midscale Error Midscale Error Match Negative Full-Scale Error Negative Full-Scale Error Match ANALOG INPUT Fully Differential Input Range (VIN+ and VIN-) Common-Mode Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage Range VREF Input Current VREF Output Voltage Min 78 77 TBD TBD -84 -76 -100 -100 3.5 40 16 110 77 14 2 0.99 10 6 10 6 10 6 VCM VREF/2 0.5 0.5 32 8 2.048 + 0.1 0.3 2.038 2.043 6 100 50 60 1 TBD 1.9 5 Typ Max Unit dB dB dB dB fa = 1 MHz + 50 kHz, fb = 1 MHz - 50 kHz dB dB dB dB ns ps ps MHz MHz Bits LSB LSB LSB LSB LSB LSB LSB LSB V V A pF pF V mA V V ppm/C ppm ppm V rms pF Test Conditions/Comments fIN = 1 MHz sine wave
fIN = 1 MHz, fNOISE = 100 kHz to 2.5 MHz fNOISE = 100 kHz to 2.5 MHz
@ 3 dB @ 0.1 dB
Guaranteed no missed codes to 14 bits
1 1 1
VCM = common-mode voltage, VIN+ and VIN- must remain within GND and VDD The voltage around which VIN+ and VIN- are centered When in track mode When in hold mode
VDD 0.45 2.058 2.053 20
When in reference overdrive mode 2.048 V 0.5% max @ VDD = 2.5 V 5% 2.048 V 0.25% max @ VDD = 2.5 V 5% and 25C For 1000 hours
VREF Temperature Coefficient VREF Long Term Stability VREF Thermal Hysteresis2 VREF Noise VREF Output Impedance VREF Input Capacitance
When in track
Rev. PrF | Page 3 of 20
AD7357
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE ITOTAL3 Normal Mode (Operational) Normal Mode (Static) Partial Power-Down Mode Full Power-Down Mode Power Dissipation Normal Mode (Operational) Normal Mode (Static) Partial Power-Down Mode Full Power-Down Mode
1 2
Preliminary Technical Data
Min 0.6 x VDRIVE 0.3 x VDRIVE 1 3 VDRIVE -0.2 0.2 1 5.5 Straight Binary t2 + 15 x tSCLK 30 4.2 2.25 2.25 14 6 3.5 5 36 16 9.5 16 2.75 3.6 20 7.5 4.5 40 59 21 11.5 110 Typ Max Unit V V A pF V V A pF Test Conditions/Comments
VIN = 0 V or VDRIVE
ns ns MSPS V V mA mA mA A mW mW mW W
Full-scale step input
Nominal VDD = 2.5 V Digital inputs = 0 V or VDRIVE SCLK on or off SCLK on or off SCLK on or off
SCLK on or off SCLK on or off SCLK on or off
Temperature ranges are as follows: Y grade: -40C to +125C, B grade: -40C to +85C. See the Terminology section. 3 ITOTAL is the total current flowing in VDD and VDRIVE.
Rev. PrF | Page 4 of 20
Preliminary Technical Data
TIMING SPECIFICATIONS
VDD = 2.5 V 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted. Table 3.
Parameter
fSCLK tCONVERT tQUIET t2 t32 t42, 3
AD7357
Limit at TMIN, TMAX
50 80 t2 + 15 x tSCLK 5 5 6
Unit
kHz min MHz max ns max ns min ns min ns max
Description
tSCLK = 1/fSCLK Minimum time between end of serial read and next falling edge of CS CS to SCLK setup time Delay from CS until SDATAA and SDATAB are three-state disabled Data access time after SCLK falling edge
12.5 11 9.5 9
t5 t6 t72 t8 t9 t102 Latency
1 2 3
ns max ns max ns max ns max
ns min ns min ns min ns max ns min ns min ns max 1 conversion latency
1.8 V VDRIVE < 2.25 V 2.25 V VDRIVE < 2.75 V 2.75 V VDRIVE < 3.3 V 3.3 V VDRIVE 3.6 V
SCLK low pulse width SCLK high pulse width SCLK to data valid hold time CS rising edge to SDATAA, SDATAB, high impedance CS rising edge to falling edge pulse width SCLK falling edge to SDATAA, SDATAB, high impedance SCLK falling edge to SDATAA, SDATAB, high impedance
5 5 3.5 9.5 5 4.5 9.5
Temperature ranges are as follows: Y grade: -40C to +125C, B grade: -40C to +85C. Specified with a load capacitance of 10 pF on SDATAA and SDATAB. The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrF | Page 5 of 20
AD7357 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter VDD to AGND, DGND, REFGND VDRIVE to AGND, DGND, REFGND VDD to VDRIVE AGND to DGND to REFGND Analog Input Voltages1 to AGND Digital Input Voltages2 to DGND Digital Output Voltages3 to DGND Input Current to Any Pin Except Supplies4 Operating Temperature Range Y Grade B Grade Storage Temperature Range Junction Temperature TSSOP Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10 to 30 sec) ESD
1 2
Preliminary Technical Data
Rating -0.3 V to +3 V -0.3 V to +5 V -5 V to +3 V -0.3 V to +0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDRIVE + 0.3V -0.3 V to VDRIVE + 0.3 V 10 mA -40C to +125C -40C to +85C -65C to +150C 150C 143C/W 45C/W 255C 2 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Analog input voltages are VINA+, VINA-, VINB+, VINB-, REFA, and REFB. Digital input voltages are CS and SCLK. 3 Digital output voltages are SDATAA and SDATAB. 4 Transient currents of up to 100 mA do not cause SCR latch up.
Rev. PrF | Page 6 of 20
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VINA+ 1 VINA-
2 16 15
AD7357
VDRIVE SCLK SDATAA SDATAB DGND AGND CS VDD
07757-002
REFA 3 REFGND 4 AGND 5 REFB 6 VINB- VINB+
7 8
AD7357
TOP VIEW (Not to Scale)
14 13 12 11 10 9
Figure 2.
Table 5. Pin Function Descriptions
Pin No. 1, 2 3, 6 Mnemonic VINA-, VINA+ REFA, REFB Description Analog Inputs of ADC A. These analog inputs form a fully differential pair. Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 F capacitor. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V +100 mV to VDD. Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input signals and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Inputs of ADC B. These analog inputs form a fully differential pair. Power Supply Input. The VDD range for the AD7357 is 2.5 V 10%. The supply should be decoupled to AGND with a 0.1 F capacitor and a 10 F tantalum capacitor. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7357 and framing the serial data transfer. Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by a trailing zero. The data is provided MSB first. If CSis held low for 18 SCLK cycles rather than 16, then two further trailing zeros appear after the 14 bits of data. If CSis held low for a further 18 SCLK cycles on either SDATAA or SDATAB , the data from the other ADC follows on the SDATA pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB. Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This clock is also used as the clock source for the conversion process. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD.
4
REFGND
5, 11
AGND
7, 8 9 10 12
VINB-, VINB+ VDD CS DGND
13, 14
SDATAB, SDATAA
15 16
SCLK VDRIVE
Rev. PrF | Page 7 of 20
AD7357 TYPICAL PERFORMANCE CHARACTERISTICS
0 -20 -40 -60
(dB)
Preliminary Technical Data
-80 -100 -120 -140 0 250 500 750 1000 1250 1500 1750 2000 FREQUENCY (kHz)
Figure 3. Typical FFT Figure 6. Histogram of Codes
1.0 0.8 0.6
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 4000 8000 CODE 12,000 16,000
07757-004
-1.0
Figure 4. Typical DNL
1.5
07757-003
Figure 7. SNR vs. Analog Input Frequency
1.0
INL ERROR (LSB)
0.5
0
-0.5
-1.0
0
4000
8000 CODE
12,000
16,000
Figure 5. Typical INL Figure 8. PSRR vs. Supply Ripple with No Supply Decoupling
Rev. PrF | Page 8 of 20
07757-005
-1.5
Preliminary Technical Data
AD7357
Figure 9. VREF vs. Reference Output Current Drive
Figure 12 Access Time vs. VDRIVE
Figure 10. Linearity Error vs. SCLK Frequency
Figure 13 Hold Time vs. VDRIVE
Figure 11. Linearity Error vs. External VREF
Rev. PrF | Page 9 of 20
AD7357 TERMINOLOGY
Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (1 LSB below the first code transition) and full scale (1 LSB above the last code transition). Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Negative Full-Scale Error Negative full-scale error is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal (that is, -VREF + 0.5 LSB) after the midscale error has been adjusted out. Negative Full-Scale Error Match Negative full-scale error match is the difference in negative fullscale error between the two ADCs. Midscale Error Midscale error is the deviation of the midscale code transition (011 ... 111) to (100 ... 000) from the ideal (that is, 0 V). Midscale Error Match Midscale error match is the is the difference in midscale error between the two ADCs. Positive Full-Scale Error Positive full-scale error is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, VREF - 1.5 LSB) after the midscale error has been adjusted out. Positive Full-Scale Error Match Positive full-scale error match is the difference in positive fullscale error between the two ADCs. ADC-to-ADC Isolation ADC-to-ADC isolation is a measure of the level of crosstalk between ADC A and ADC B. It is measured by applying a fullscale 1 MHz sine wave signal to one of the two ADCs and applying a full-scale signal of variable frequency to the other ADC. The ADC-to-ADC isolation is defined as the ratio of the power of the 1 MHz signal on the converted ADC to the power of the noise signal on the other ADC that appears in the FFT. The noise frequency on the unselected channel varies from 100 kHz to 2.5 MHz. Power Supply Rejection Ratio (PSRR) PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. The frequency of the input varies from 5 kHz to 25 MHz. PSRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output.
Rev. PrF | Page 10 of 20
Preliminary Technical Data
Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN- of frequency, fS, as CMRR (dB) = 10log (Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) dB Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit converter, SINAD is 86 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7357, it is defined as
THD (dB ) = -20 log
V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 V1
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.
Preliminary Technical Data
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb).
AD7357
sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.
Thermal Hysteresis Thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either
T_HYS+ = 25C to TMAX to 25C T_HYS- = 25C to TMIN to 25C It is expressed in ppm using the following equation:
VHYS ( ppm) = VREF (25C ) - VREF (T _ HYS) x 10 6 VREF (25C )
The AD7357 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms
where: VREF(25C) is VREF at 25C VREF(T_HYS) is the maximum change of VREF at T_HYS+ or T_HYS-.
Rev. PrF | Page 11 of 20
AD7357 THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7357 is a high speed, dual, 14-bit, single-supply, successive approximation analog-to-digital converter. The part operates from a 2.5 V power supply and features throughput rates up to 4.2 MSPS. The AD7357 contains two on-chip differential track-and-hold amplifiers, two successive approximation analog-to-digital converters, and a serial interface with two separate data output pins. The part is housed in a 16-lead TSSOP package, offering the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part, but also provides the clock source for each successive approximation ADC. The AD7357 has an on-chip 2.048 V reference. If an external reference is desired the internal reference can be overdriven with a reference of value ranging from (2.048 V + 100 mV) to VDD. If the internal reference is to be used elsewhere in the system, then the reference output needs to be buffered first. The differential analog input range for the AD7357 is VCM VREF/2. The AD7357 features power-down options to allow power saving between conversions. The power-down feature is implemented via the standard serial interface, as described in the Modes of Operation section.
Preliminary Technical Data
DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN- pins must be matched, otherwise the two inputs have different settling times, resulting in errors.
CAPACITIVE DAC B VIN+ A SW1 A B CAPACITIVE DAC
07757-009
CS
COMPARATOR
VIN-
SW2
CS
SW3
CONTROL LOGIC
VREF
Figure 15. ADC Conversion Phase
ANALOG INPUT STRUCTURE
Figure 16 shows the equivalent circuit of the analog input structure of the AD7357. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The C1 capacitors in Figure 16 are typically 8 pF and can primarily be attributed to pin capacitance. The R1 resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 30 . The C2 capacitors are the ADC's sampling capacitors with a capacitance of 32 pF typically.
VDD D VIN+ C1 D
CONVERTER OPERATION
The AD7357 has two successive approximation ADCs, each based around two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of one of these ADCs in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 14 (the acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays may acquire the differential signal on the input.
CAPACITIVE DAC B VIN+ A SW1 A B VREF CAPACITIVE DAC
07757-008
R1 C2
CS
COMPARATOR
VIN-
SW2
CS
SW3
CONTROL LOGIC
VDD D VIN- C1 D
07757-010
R1 C2
Figure 14. ADC Acquisition Phase
Figure 16.Equivalent Analog Input Circuit, Conversion Phase--Switches Open, Track Phase--Switches Closed
When the ADC starts a conversion (Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution
For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the analog input pins. In applications where
Rev. PrF | Page 12 of 20
Preliminary Technical Data
harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 17 shows a graph of the THD vs. the analog input signal frequency for various source impedances.
AD7357
performance. Figure 19 defines the fully differential input of the AD7357.
VREF p-p COMMONMODE VOLTAGE
*ADDITIONAL
VIN+
AD7357*
VREF p-p VIN-
07757-013
PINS OMITTED FOR CLARITY.
Figure 19. Differential Input Definition
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins in each differential pair (VIN+ - VIN-). VIN+ and VIN- should be simultaneously driven by two signals each of amplitude VREF that are 180 out of phase. This amplitude of the differential signal is, therefore -VREF to +VREF peak-to-peak regardless of the common mode (CM). The common mode is the average of the two signals and is therefore the voltage on which the two inputs are centered. CM = (VIN+ + VIN-)/2 This results in the span of each input being CM VREF/2. This voltage has to be set up externally. When setting up the CM, ensure that that VIN+ and VIN- remain within GND/VDD. When a conversion takes place, common mode is rejected resulting in a virtually noise free signal of amplitude -VREF to +VREF corresponding to the digital codes of 0 to 16383 for the AD7357.
Figure 17. THD vs. Analog Input Frequency for Various Source Impedances
DRIVING DIFFERENTIAL INPUTS
Differential operation requires VIN+ and VIN- to be driven simultaneously with two equal signals that are 180 out of phase. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversions.
Figure 18 shows a graph of the THD vs. the analog input frequency while sampling at 4.2 MSPS. In this case, the source impedance is 33 .
Differential Amplifier
An ideal method of applying differential drive to the AD7357 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. Figure 20 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components.
Figure 18. THD vs. Analog Input Frequency
ANALOG INPUTS
Differential signals have some benefits over single-ended signals, including noise immunity based on the devices common-mode rejection and improvements in distortion
Rev. PrF | Page 13 of 20
AD7357
If the analog inputs source being used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) should be the same. If the source has a 50 impedance and a 50 termination, for example, the value of RG2 should be increased by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. The outputs of the amplifier are perfectly matched balanced differential outputs of identical amplitude and are exactly 180 out of phase.
C F1 RF1 RG1 +2.048V GND -2.048V 51 VOCM RG2 RS* 2.048V 1.024V 0V VIN+
20k 2 x VREF p-p VREF GND 440
Preliminary Technical Data
into a Differential Signal
220 V+ 27 2.048V 1.024V 0V VIN+
V- 220 220 V+ 27 2.048V 1.024V 0V
AD7357*
VIN- REFA/REFB
A
V-
10k 10F
07757-016
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD8138
RS* R F2 C F2 10k 2.048V 1.024V 0V VIN-
AD7357
REFA/REFB
Figure 22. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Unipolar Signal
ADC TRANSFER FUNCTION
10F
10k
The output coding for the AD7357 is straight binary. The designed code transitions occur at successive LSB values (such as, 1 LSB, 2 LSBs). The LSB size is (2 x VREF)/16384. The ideal transfer characteristic of the AD7357 is shown in Figure 23.
07757-014
*MOUNT AS CLOSE TO THE AD7357 AS POSSIBLE AND ENSURE HIGH PRECISION RS RESISTORS ARE USED. RS - 33; RG1 = RF1 = RF2 = 499; CF1 = CF2 = 39pF; RG2 = 523.
Figure 20. Using the AD8138 as a Single-Ended-to-Differential Amplifier
ADC CODE
111 ... 111 111 ... 110 111 ... 101
Op Amp Pair
An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7357. The circuit configurations shown in Figure 21 and Figure 22 show how an op amp pair can be used to convert a single-ended signal into a differential signal for a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference. The AD8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7357.
2 x VREF p-p VREF GND V- 220 220 V+ 27 2.048V 1.024V 0V 440 220 V+ 27 2.048V 1.024V 0V VIN+
000 ... 010 000 ... 001 000 ... 000 -VREF + 1 LSB -VREF + 0.5 LSB ANALOG INPUT +VREF - 1 LSB +VREF - 1.5 LSB
07757-017
Figure 23. AD7357 Deal Transfer Characteristic
AD7357*
VIN- REFA/REFB
A
V-
10k 10F
07757-015
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
Rev. PrF | Page 14 of 20
Preliminary Technical Data MODES OF OPERATION
The mode of operation of the AD7357 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. After a conversion has been initiated, the point at which CS is pulled high determines which power-down mode, if any, the device enters. Similarly, if already in a power-down mode, CS can control whether the device returns to normal operation or remains in a power-down mode. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements.
AD7357
Once a data transfer is complete and SDATAA and SDATAB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again (assuming the required acquisition time has been allowed).
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7357 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffers. To enter partial power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 25. Once CS has been brought high in this window of SCLKs, the part enters partial power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATAA and SDATAB go back into threestate. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line.
CS
1 2 10 14
NORMAL MODE
Normal mode is intended for applications needing the fastest throughput rates. The user does not have to worry about any power-up times because the AD7357 remains fully powered at all times. Figure 24 shows the general diagram of the operation of the AD7357 in this mode.
CS
1 10 14
SCLK
07757-018
DOUTA DOUTB
LEADING ZEROS + CONVERSION RESULT
Figure 24. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as described in the Serial InterfaceError! Reference source not found. section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 16th SCLK falling edge, the part remains powered up, but the conversion is terminated and SDATAA and SDATAB go back into three-state. 16 serial clock cycles are required to complete the conversion and access the conversion result for the AD7357. The SDATA lines do not return to three-state after 16 SCLK cycles have elapsed, but instead do so when CS is brought high again. If CS is left low for another 2 SCLK cycles, two trailing zeros are clocked out after the data. If CS is left low for a further 16 SCLK cycles, the result for the other ADC on board is also accessed on the same SDATA line as shown in Figure 31 (see the Serial Interface section). Once 32 SCLK cycles have elapsed, the SDATA line returns to three-state on the 32nd SCLK falling edge. If CS is brought high prior to this, the SDATA line returns to three-state at that point. Thus, CS may idle low after 32 SCLK cycles until it is brought high again sometime prior to the next conversion if so desired, because the bus still returns to three-state upon completion of the dual result read.
SCLK
07757-019
DOUTA DOUTB
THREE-STATE
Figure 25. Entering Partial Power-Down Mode
To exit this mode of operation and power up the AD7357 again, perform a dummy conversion. On the falling of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after approximately 200 ns has elapsed (or one full conversion), and valid data results from the next conversion, as shown in Figure 26. If CS is brought high before the second falling edge of SCLK, the AD7357 again goes into partial power-down mode. This avoids accidental power-up due to glitches on the CS line. Although the device may begin to power up on the falling edge of CS, it powers down again on the rising edge of CS. If the AD7357 is already in partial powerdown mode and CS is brought high between the second and 10th falling edges of SCLK, the device enters full power-down mode.
Rev. PrF | Page 15 of 20
AD7357
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substantially longer than that from a partial power-down. This mode is more suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus, power-down. When the AD7357 is in full power-down, all analog circuitry is powered down. Full power-down is entered in a similar way as partial power-down, except that the timing sequence shown in Figure 25 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the
THE PART BEGINS TO POWER UP.
Preliminary Technical Data
10th falling edge of SCLK. The device enters partial power-down mode at this point. To reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in Figure 27. Once CS has been brought high in this window of SCLKs, the part completely powers down. Note that it is not necessary to complete the 16 SCLKs once CS has been brought high to enter a power-down mode. To exit full power-down mode and power-up the AD7357, perform a dummy conversion, such as powering up from partial power-down. On the falling edge of CS, the device begins to power up, as long as CS is held low until after the falling edge of the 10th SCLK. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 28.
THE PART IS FULLY POWERED UP; SEE POWER-UP TIMES SECTION.
tPOWER-UP1
CS
1 10 14
SCLK
1
14
DOUTA DOUTB
INVALID DATA
VALID DATA
Figure 26. Exiting Partial Power-Down Mode
THE PART ENTERS PARTIAL POWER DOWN. CS
THE PART BEGINS TO POWER UP.
THE PART ENTERS FULL POWER DOWN.
SCLK
1
2
10
14
1
2
10
14
DOUTA DOUTB
INVALID DATA
THREE-STATE
INVALID DATA
THREE-STATE
Figure 27. Entering Full Power-Down Mode
THE PART BEGINS TO POWER UP. CS
THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION.
tPOWER-UP2
SCLK
1
10
14
1
14
DOUTA DOUTB
INVALID DATA
VALID DATA
Figure 28. Exiting Full Power-Down Mode
Rev. PrF | Page 16 of 20
07757-022
07757-021
07757-020
Preliminary Technical Data
POWER-UP TIMES
The AD7357 has two power-down modes: partial power-down and full power-down. There are described in detail in the Partial Power-Down Mode and Full Power-Down Mode sections. This section deals with the power-up time required when coming out of either of these modes. It should be noted that the power-up times apply with the recommended decoupling capacitors in place on the REFA and REFB pins. To power up from partial power-down mode, one dummy cycle is required. The device is fully powered up after approximately 200 ns from the falling edge of CS has elapsed. Once the partial power-up time has elapsed, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. To power up from full power-down, approximately 6 ms should be allowed from the falling edge of CS, shown in Figure 28 as tPOWER-UP2. Note that during power-up from partial power-down mode, the track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first SCLK edge that the part receives after the falling edge of CS. When power supplies are first applied to the AD7357, the ADC can power up in either of the power-down modes or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the part is to be kept in partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; in the second cycle, CS must be brought high between the second and 10th SCLK falling edges (see Figure 25).
Figure 29. Power vs. Throughput Rate
AD7357
Alternatively, if the part is to be placed into full power-down mode when the supplies are applied, three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; the second and third dummy cycles place the part into full power-down mode (see Figure 27 and the Full Power-Down Mode section).
POWER vs. THROUGHPUT RATE
The power consumption of the AD7357 varies with the throughput rate. When using very slow throughput rates and as fast an SCLK frequency as possible, the various powerdown options can be used to make significant power savings. However, the AD7357 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or if it is scaled with the sampling rate. Figure 29 shows a plot of power vs. throughput rate when operating in normal mode for a fixed maximum SCLK frequency and an SCLK frequency that scales with the sampling rate. The internal reference was used for Figure 29.
Rev. PrF | Page 17 of 20
AD7357 SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial interfacing to the AD7357. The serial clock provides the conversion clock and controls the transfer of information from the AD7357 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode at which point the analog input is sampled and the bus is taken out of three-state. The conversion is also initiated at this point and requires a minimum of 16 SCLKs to complete. Once 15 SCLK falling edges have elapsed, the track and hold goes back into track on the next SCLK rising edge, as shown in Figure 30 at Point B. On the rising edge of CS, the conversion will be terminated and SDATAA and SDATAB go back into three-state. If CS is not brought high, but is instead held low for a further 16 SCLK cycles on SDATAA, the data from the conversion on ADCB are output on SDATAA. Likewise, if CS is held low for a further 16 SCLK cycles on SDATAA, the data from the conversion on ADC A is output on SDATAB (see Figure 31). In this case, the SDATA line in use
Preliminary Technical Data
goes back into three-state on the 32nd SCLK falling edge or the rising edge of CS, whichever occurs first. A minimum of 16 serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the AD7357. CS going low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Thus, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The 14-bit result then follows with the final bit in the data transfer valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge depending on the SCLK frequency. The first rising edge of SCLK after the CS falling edge would have the second leading zero provided, and the 15th rising SCLK edge would have DB0 provided.
tACQUISITION
CS
tCONVERT t2
SCLK
1 2 3 4
t9
B
t6
5 15 16
Figure 30. Serial Interface Timing Diagram
CS
t2
SCLK
1 2 3 4
t6
5 15 16 17 18 31 32
t3
DOUTA THREESTATE 2 LEADING ZEROS 0 0 DB13 A DB12 A
t4
DB11A
t5
t7
DB0A 2 ZEROS 0 0 DB13 B DB12 B DB1B DB0B 0
07757-025
THREESTATE
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
Rev. PrF | Page 18 of 20
07757-024
DOUTA DB13 0 0 DOUTB THREESTATE 2 LEADING ZEROS
t3
t4
DB12 DB11
t7
DB10 DB2
t5
DB1 DB0 0
t8 tQUIET
THREE-STATE
Preliminary Technical Data APPLICATION HINTS
GROUNDING AND LAYOUT
The analog and digital supplies to the AD7357 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AD7357 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. The two AGND pins of the AD7357 should be sunk in the AGND plane. Digital and analog ground plans should be joined in only one place. If the AD7357 is in a system where multiple devices require an AGND and DGND connection, the connection should still be made at one point only. A star ground point that should be established as close as possible to the ground pins on the AD7357. Avoid running digital lines under the device because this couples noise onto the die. The analog ground planes should be allowed to run under the AD7357 to avoid noise coupling. The power supply lines to the AD7357 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, fast switching signals such as clocks, should be shielded with digital ground, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A
AD7357
microstrip technique is the best method, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is important; all supplies should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to logic switching.
EVALUATING THE AD7357 PERFORMANCE
The recommended layout for the AD7357 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the converter evaluation and development board (CED). The CED can be used in conjunction with the AD7357 evaluation board (as well as many other evaluation boards ending in the ED designator from Analog Devices, Inc.) to demonstrate/evaluate the ac and dc performance of the AD7357. The software allows the user to perform ac (fast Fourier transform) and dc (linearity) tests on the AD7357. The software and documentation are on a CD shipped with the evaluation board.
Rev. PrF | Page 19 of 20
AD7357 OUTLINE DIMENSIONS
5.10 5.00 4.90
Preliminary Technical Data
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7357BRUZ1 AD7357BRUZ-500RL71 AD7357BRUZ-RL1 AD7357YRUZ1 AD7357YRUZ-500RL71 AD7357YRUZ-RL1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07757-0-11/08(PrF)
Rev. PrF | Page 20 of 20

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